Design of a high efficiency CdS/CdTe solar cell with optimized step doping, film thickness, and carrier lifetime of the absorption layer

A high-efﬁciency CdS/CdTe solar cell with step doped absorber layer, optimized back surface ﬁeld layer, and long carrier lifetime in the absorption layer was designed. At ﬁrst, The CdS/CdTe reference cell is simulated and compared with previous experimental data. In order to obtain the highest efﬁciency, the thickness and step doping of the absorber and back surface ﬁeld layer were optimized. In addition, the effect of carrier lifetime variation in the CdTe layer on the conversion efﬁciency of CdTe cell was investigated. Compared with reference cell, Efﬁciency enhancement of the proposed structure was 4.44%. Under global AM 1.5 conditions, the optimized cell structure had an open-circuit voltage of 0.987 V, a short-circuit current density of 27.9 mA/cm 2 and a ﬁll factor of 82.4%, corresponding to a total area conversion efﬁciency of 22.76%.


INTRODUCTION
Third generation thin-film solar cells are the most promising field of photovoltaic solar cell research.They are much cheaper to manufacture (due to using simpler deposition processes), and require much less materials, as compared to the conventional single-crystal cells.Polycrystalline CdTe films have high optical absorption coefficient and are normally used in a CdS/CdTe heterojunction configuration.The most important parameter that affects photon absorption is thickness of the CdTe layer [1].A ZnTe layer is usually used as a back surface barrier to repel the electrons at the CdTe/ZnTe heterojunction and thus decrease the loss of carriers at the back contact (due to presence of a higher band-gap layer at the back) [2].This layer also reduces carrier recombination at the back contact due to the barrier (i.e.conduction band discontinuity) for electrons at the interface between CdTe and ZnTe layers.The electrons will reflect at this interface and will be collected with a higher probability at the CdS/CdTe heterojunction.Highly n-type CdS films are used as a suitable window layer for these cells.The thickness of CdS affects the cell's conversion efficiency.Up to a certain point, thinner CdS films produce higher short-circuit current densities [3].
The record cell efficiency of CdTe solar cells were increased by only 1.5% during the last 17 years [4]- [8].Previous groups reported a maximum cell efficiency of 16.5% [9]- [12], but recently, First Solar research group reported a cell efficiency of 20.4% (verified by NREL) and a module efficiency of 13.9% was obtained under the lab conditions [13].
Fabrication of high-efficiency CdS/CdTe solar cells with ultra-thin (i.e.below 1 µm) absorber layers is a challenging yet highly desirable step in improving the cell performance.Thicker absorber layers are generally used to avoid pinholes reaching through to the window layer, which may lead to shorting to the back contact.Typically, the cell performance decreases due to shunting, incomplete absorption (deep penetration loss), fully depleted CdTe layer, or interference between the main and the back contact junctions when the CdTe layer thickness approaches a certain limit.Recently N. R. Paudel et al. [14] concluded that with comprehensive cleaning of the substrates, very thin absorber layers (with only 0.25 µm of CdTe) without pinhole shorting could be deposited.
Simulation of CdTe thin film solar cells is an important strategy to test the viability of proposed structures and to predict the effect of physical changes on the cell performance.Nowadays, the challenge facing researchers and technologists is how to increase the efficiency of CdS/CdTe solar cells and therefore, decrease the gap between actual efficiency and the theoretical limit.This paper first investigates an already-fabricated and simulated CdTe/CdS cell structure as a reference cell [2], and compares all of the simulation results with this reference cell.The improvement of the efficiency of new structures with different thicknesses of CdTe and ZnTe layers were investigated and compared to the reference cell.The effect of stepped doping grading of the BSF layer on the characteristics of the CdTe/CdS solar cells was also studied.By analyzing electrical characteristics of the new structure, optimum doping for the BSF layer (for achieving the highest efficiency) was obtained.Furthermore, in order to further increase the open-circuit voltage, the effect of carrier lifetime was studied.All of the simulations were done using Silvaco software [15].These improvements resulted in a considerable improvement in the cell efficiency, as compared to the reference sample.

COMPARISON WITH PREVIOUS DATA
The main objective in this work was to obtain high efficiency with a reduced CdTe absorber layer thickness and to replace ZnTe layer by two layers (with different doping concentrations) in the reference CdS/CdTe cell [2].The reference cell structure which is named structure (a) is schematically shown in Figure 1.
In the reference cell, the layers were composed of 50 nm CdS, 200 nm CdS 1−x Te x (as mixed CdS/CdTe layer), 1 µm CdTe, and 200 nm ZnTe.
But there was no ITO coated glass in the reference cell.Therefore, we considered an ITO layer as transparent conducting oxide in the reference cell structure.Subsequently, this cell was modeled and its simulated characteristics were obtained.
Under AM 1.5 conditions, considering the ITO coated glass, this cell had open-circuit voltage of 925 mV, short-circuit current density of 24.82 mA/cm 2 , fill factor of 0.798, and conversion efficiency of 18.32%.The ITO coated glass added in all simulations.Some of the most important parameters used in the simulations are shown in Table 1 [1,2].

INVESTIGATION OF THICKNESS OF ZNTE LAYER ON THE CDTE CELL PERFORMANCE
Improvement of cell efficiency for different thicknesses of CdTe and ZnTe layers (corresponding to a total thickness of the CdTe and ZnTe thickness in the reference cell) was investigated.Figure 2 shows the efficiency of the cell as a function of ZnTe thickness layer.
As Figure 2 shows, at first, the device efficiency increases with increasing ZnTe thickness.This is due to enhanced absorption in the long wavelengths region.Then, after reaching a peak at about 0.8 µm the efficiency decreases, due to lower absorption in the ultra-thin CdTe layer.With these optimized thicknesses (0.8 µm ZnTe and 0.4 µm CdTe), the proposed cell showed an improved efficiency of 19.81%.The resulted structure with the optimized ZnTe thickness, which is named structure (b), is shown in Figure 3.
For comparison, characteristics of the reference cell and the structure with optimized absorber layers are shown in Fig- ure 4. Accordingly, increasing the ZnTe thickness should improve the performance (by achieving a high J SC ) and at the same time, increasing V OC (due to increasing absorption in the long wavelength region).

INVESTIGATION OF DOPANT PROFILING AND THICKNESS OF ZNTE LAYER ON CELL PERFORMANCE
In the next stage, a built-in electrical field was formed in the ZnTe layer by step-doping grading, which resulted in an in-   crease in the efficiency of the CdS/CdTe/ZnTe cell.This field assists carrier migration and therefore, reduces the series resistance of the cell, as well as the charge storage time.To achieve this, the ZnTe layer was divided into two layers with different doping levels.These layers were 0.6 µm thick with 10 14 -10 18 cm −3 doping concentration (top layer) and 0.2 µm thick (reference cell default) with 10 18 cm −3 doping concentration (bottom layer).This structure, which is named structure (c), is shown in Figure 5.

CdS
In this structure, doping of top ZnTe layer was varied from 10 14 cm −3 to 10 18 cm −3 .Figure 6 shows the variation of the doping concentration of the top ZnTe layer when the doping of the ZnTe bottom layer was fixed.The efficiency was first increased with doping concentration of top ZnTe layer and then decreased after reaching 10 16 cm −3 concentration.The efficiency was highest for 10 16 cm −3 doping concentration due to both high built-in electrical field and high absorption level.Before this optimum level, built-in electrical field is high but absorption is low and after that, built-in electrical field is low but absorption is high.
Figure 7 shows the J-V characteristics and power curve of the reference cell and the stepped doping structure.It shows a clear improvement in V OC and J SC of the cell with step doping design.
In the next set of simulations for more advanced results, step doping strategy was also applied to the top ZnTe layer.For this purpose, top ZnTe layer (0.6 µm thick) was divided into two layers with the same thickness, and efficiency of the cell was evaluated by variation of their doping concentrations (from 10 14 cm −3 to 10 18 cm −3 ). Figure 8 shows the proposed structure, which is named structure (d), for this set of simulations.
The variation of the cell efficiency for different doping of top ZnTe layers (i.e. two 300 nm thick layers) is shown in Figure 9.
As it can be seen from this Figure, the efficiency does not increase by the step doping of the top ZnTe layer and it is maximum for 10 16 cm −3 doping concentration of the two 300 nm thick ZnTe layers.Therefore, the cell efficiency does not increase by dividing the 600 nm thick ZnTe layer into two 300 nm thick layers.

CARRIER LIFETIME IN CDTE LAYER
The carrier lifetime of CdTe, which is the key parameter for the voltage calculations, also has a strong influence on the solar cell fill-factor.In order to improve the efficiency further, the basic parameters (J SC , V OC , FF and Efficiency) of the proposed cell were obtained as a function of carrier lifetime in the CdTe layer.The results are shown in Figure 10.The variations of carrier lifetime in the model were obtained with variation of defect density.
Increased defect density and purity of the CdTe alters the electron lifetime as well as the hole lifetime.Physically, a reduction in the defect density could be the key to improvement in increased lifetime through a smaller number of recombination centers.
Therefore, at higher lifetimes, essentially all carriers generated in the depletion region will be collected.Consequently, the V OC and hence, the conversion efficiency, should improve with increasing the carrier lifetime.An equation for V OC is found by: Where n is the ideally factor, k Boltzmann's constant, T absolute temperature, J o dark current density, J SC short current density and q electrical charge.J o is directly linked to the defect density and purity of the material (a higher lifetime corresponds to a purer or low defect density material).With this formula, if J SC saturates, V OC can be increased if J o decreases.Obviously, as simulations predicted, longer carrier lifetimes resulted in a higher V OC .As a result, the conversion efficiency increases with increasing carrier lifetime.
Our simulation results indicated that if the carrier lifetime is equal to 10 ns [16], the efficiency can be as high as 22.76%.2.

CONCLUSION
Several step-doped profiles in the BSF layer of CdS/CdTe cells were evaluated.Optimization of the location of homojunction and doping concentrations during the step doping grading resulted in a conversion efficiency of 21.28%.This result showed a noticeable improvement over the 18.32% efficiency of the reference sample which had a uniform doping profile in the absorber layer.Subsequently, the effect of carrier lifetime in the CdTe layer on the performance of CdS/CdTe cell was investigated.The maximum conversion efficiency of 22.76% (V OC = 0.987 V, J SC = 27.9 mA/cm 2 , FF = 0.824) was achieved with the proposed cell consisting of 0.2 µm ZnTe bottom layer with 10 18 cm −3 doping concentration, 0.6 µm ZnTe top layer with 10 16 cm −3 doping concentration, 0.4 µm CdTe layer with 10 ns carrier lifetime, and 50 nm CdS layer thickness.Practically, these modifications should not be difficult to be implemented during the fabrication process.

FIG. 2 FIG. 4
FIG. 2 Variation of cell efficiency as a function of thickness of ZnTe layer.

FIG. 7 JFIG. 9
FIG.7J-V and power curves of the reference cell and stepped doping structure.

FIG. 11
FIG. 11 Current density-voltage and power output of the CdS/CdTe solar cell for three structures at 1 sun AM1.5 illumination.Structure (a) is reference cell.Structure (b) is step doped structure and structure (c1) is structure (c) with optimized step-doping grading and thickness of BSF layer and long carrier lifetime in CdTe layer.

Figure 11
Figure 11 shows J-V and power characteristics comparison between three structures under AM1.5 illumination at 1 sun.(a) is the reference cell, (b) is the step-doped cell, and (c 1 ) is the structure (c) with optimized step doping structure and optimized thickness of BSF layer, and long carrier lifetime in CdTe layer.As this Figure shows, the short current density for proposed structure (c 1 ) is as high as 27.9 mA/cm 2 corresponding to an efficiency of 22.76% due to step doping grading and long carrier lifetime in CdTe layer.For comparison, the opencircuit voltage, short-circuit current, fill factor and conversion efficiency for different structures are given in Table2.

FIG. 10
FIG. 10 Basic parameters of the cell as a function of the CdTe layer's carrier lifetime.